1. Field of the Invention
This invention relates generally to methods for manufacturing semiconductor devices. More particularly, this invention relates to techniques for fabricating semiconductor structures having reduced lateral spacing between buried regions.
2. Description of the Prior Art
The Isoplanar process as disclosed by D. Peltzer in U.S. Pat. No. 3,648,125, "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure," in which the active areas of a semiconductor wafer are separated by oxide-isolation regions has provided a significant advancement in the semiconductor manufacturing art. In accordance with the techniques disclosed by Peltzer, N-type collector/emitter regions are first formed laterally apart from one another adjacent to the top surface of a P-type semiconductor substrate. An epitaxial layer of, for example, P-type conductivity is then grown over the top surface of the substrate so that the N-type collector/emitter regions become buried regions. Grooves are then formed in the epitaxial layer at locations above portions of the substrate lying between the buried regions. The grooves are exposed to an appropriate oxidizing environment to grow electrically insulating oxide-isolation regions of silicon dioxide which extend down to the buried regions. Various other N-type and P-type regions are then formed in the remainder of the epitaxial layer to create whatever devices are desired. The oxide-isolation regions electrically isolate the devices formed in the portion of the epitaxial layer above one buried region from the devices formed in the portions of the epitaxial layer above the other buried regions.
One of the problems involved in the Isoplanar oxide-isolation process is that inversion may occur in a portion of the substrate between a pair of buried regions directly below an oxide-isolation region. That is, P-type silicon under an oxide-isolation region and between buried N-type regions may be converted to N-type silicon so as to destroy the electrical isolation between the respective buried N-type regions.
Such inversion is conventionally prevented by doping the portions of the P-type substrate directly below the oxide-isolation regions and between the buried N-type regions with a higher concentration of a P-type impurity such as boron to form "anti-inversion regions." D. O'Brien discloses one method for forming anti-inversion regions in U.S. Pat. No. 3,962,717, "Oxide Isolated Integrated Injection Logic with Selective Guard Ring." According to O'Brien, a P-type impurity is predeposited to a shallow depth in the grooves used for forming the oxide-isolation regions. As the oxide-isolation regions are grown, the predeposited P-type impurity moves ahead of the advancing silicon/silicon-dioxide interface so as to form anti-inversion regions between the buried regions. A characteristic of the O'Brien method is that the anti-inversion regions extend up the sidewalls of the oxide-isolation regions. Where the epitaxial layer is N-type, this may be disadvantageous because portions of the epitaxial layer along the sidewalls must sometimes be further doped with an N-type impurity, necessitating an extra masking step. Furthermore, the anti-inversion regions of O'Brien do not penetrate sufficiently deep into the gaps between each pair of buried regions to materially affect the breakdown voltage between buried regions. Consequently, the lateral spacing between buried regions determines the breakdown voltage and typically must be about three microns to provide a suitably high breakdown voltage.
Another method for preventing inversion below the oxide-isolation regions is to use a substrate having a substantially higher concentration of P-type dopant. This solution, however, results in a substrate-to-buried region capacitance that is often unacceptably high.
It is known that a bipolar transistor can be formed by various up-diffused base processes. For example, a P-type impurity such as boron may be introduced to a shallow depth into the top surface of a P-type substrate containing an N-type region extending to a greater depth into the substrate from its top surface. An N-type epitaxial layer is then grown on the top surface of the substrate. During the growth of the epitaxial layer and during subsequent high-temperature steps, the P-type impurity diffuses upward into the epitaxial layer to form a P-type region beginning approximately at the top surface of the substrate and extending into the N-type epitaxial layer. The up-diffused P-type region comprises the base for an NPN transistor, while the N-type buried region and the N-type epitaxial layer form the emitter and collector, respectively.